Design of low-power, high-speed approximate 4:2 compressors for efficient partial product reduction in multipliers

Abstract

Partial product reduction becomes the main task in the multiplication process. Therefore, the partial product stages of multipliers are reduced with the usage of compressors, by using compressors in the multiplier. Using compressors in the multiplier circuit significantly impacts multiplier performance. Approximate compressors are crucial for achieving better design metrics in parallel multipliers. This paper proposes to create various new approximate 4:2 compressor circuits. A trade-off is made between the performance and accuracy of this approximate circuit design approach. The proposed designs have been implemented using XOR-XNOR gates with a 2-to-1 multiplexer, and also XOR-XNOR gates with transmission gates. All these circuits have been simulated using Cadence in different technological nodes. Compared with the existing technique, the proposed 4:2 approximation compressor provides 51.4% power reduction and 26.45% delay reduction for 45 nm equipment.