Optimized mapping in 2D and 3D network on chip using Bat algorithm

Abstract

Communication within system-on-chip (SoC) architectures has evolved significantly to keep pace with the growing complexity of modern applications. To overcome the limitations of traditional interconnects, network-on-chip (NoC) has emerged as a scalable and efficient communication solution. Although early NoC designs relied heavily on 2D architectures, their physical and performance constraints have led to the rise of 3D NoC architectures, which offer better spatial integration and improved performance. In order to automate the NoC design process, a number of electronic design automation (EDA) tools and optimization algorithms are employed to help designers achieve efficient and high-performance designs. Within this EDA framework, one of the most critical stages is the core placement or application mapping phase, where computational tasks are allocated to the processing elements of the architecture. This step is very hard due to its combinatorial nature, and its optimization is essential since it directly impacts communication cost, energy consumption, and overall system performance. To address this challenge, numerous heuristic and metaheuristic algorithms have been explored for both 2D and 3D NoCs. In this paper, we propose an adaptation of the bat algorithm to solve the mapping problem in both 2D and 3D NoC architectures, with the objective of minimizing communication cost. The proposed approach is evaluated and compared against other optimization methods to assess its effectiveness in enhancing NoC performance within the EDA framework.