Vector-logic models of digital circuits for simulation and rendering

Abstract

Vector-logical in-memory computing for solving modelling for simulation (MOSI) problems by using read-write transactions free of processor instructions is proposed. A parser mechanism has been developed for converting the HDL code of the logical circuit into the internal vector-logical data structures of the MOSI service, addresses of logical vectors of elements. Deductive vectors are generated from the vector-logic model of the digital circuit for fault as address simulation of the input test sets. A mechanism for modelling a fault simulation matrix as the addresses of the deductive vector bits of each element on the test set has been created. The results of good-value and fault as address simulation are rendered and synchronized in the good-value simulation, fault as address simulation, fault simulation matrices on the input set, and on the lines of the logical circuit displayed on the monitor. Modeling and simulation mechanisms encoded and verified using examples of logical circuits of the ISCAS library. The scientific novelty is represented by vector-logical models of digital circuit elements, good-value simulation of test set as address and fault as address simulation of a digital circuit, and fault as address simulation of the input set, using a quadratic simulation matrix.